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CD40100BMS
December 1992
CMOS 32-Stage Static Left/Right Shift Register
Description
CD40100BMS is a 32-Stage shift register containing 32 D-type master-slave flip-flops. The data present at the SHIFT RIGHT INPUT is transferred into the first register stage synchronously with the positive CLOCK edge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCULATE CONTROL is at a high level, and the CLOCK INHIBIT is low. If the LEFT/RIGHT CONTROL is at a high level and the RECIRCULATE CONTROL is also high, data at the SHIFT LEFT INPUT is transferred into the 32nd register stage synchronously with the positive CLOCK transition, provided the CLOCK INHIBIT is low. The state of the LEFT/RIGHT CONTROL, RECIRCULATE CONTROL, and CLOCK INHIBIT should not be changed when the CLOCK is high. Data is shifted one stage left or one stage right depending on the state of the LEFT/RIGHT CONTROL, synchronously with the positive CLOCK edge. Data clocked into the first or 32nd register states is available at the SHIFT LEFT or SHIFT RIGHT OUTPUT respectively, on the next negative CLOCK transition (see Data Transfer Table). No shifting occurs on the positive CLOCK edge if the CLOCK INHIBIT line is at a high level. With the RECIRCULATE CONTROL low, data in the 32nd stage is shifted into the first stage when the LEFT/ RIGHT CONTROL is low and from the first stage to the 32nd stage when the LEFT/RIGHT CONTROL is low, and from the first state to the 32nd stage when the LEFT/RIGHT control is high. The CD40100BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H2R H6W
Features
* High Voltage Type (20V Rating) * Fully Static Operation * Shift Left/Shift Right Capability * Multiple Package Cascading * Recirculate Capability * LIFO of FIFO Capability * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Standardized, Symmetrical Output Characteristics * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Applications
* Serial Shift Registers * Time Delay Circuits * Expandable N-Bit Data Storage Stack (LIFO Operation)
Pinout
CD40100BMS TOP VIEW
Functional Diagram
LEFT/RIGHT CONTROL NC 1 2 3 4 5 6 7 8 16 VDD 15 NC 14 NC LEFT/RIGHT CONTROL 12 SHIFT RIGHT OUT 13 11 SHIFT RIGHT IN 10 NC 9 RECIRCULATE CONTROL IN CLOCK 4 CLOCK INHIBIT 2 SHIFT LEFT 6 9 RECIRCULATE CONTROL VSS = 8 VDD = 16 NC = 1, 5, 7, 10, 14, 15 SHIFT LEFT 4 OUT IN SHIFT RIGHT 11 13 SHIFT RIGHT 12 OUT
CLOCK INHIBIT CLOCK SHIFT LEFT OUT NC SHIFT LEFT IN NC VSS
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3349
7-1277
Specifications CD40100BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
VOH > VOL < VDD/2 VDD/2
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1278
Specifications CD40100BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25 C +125oC, -55oC +25oC +125 C, -55 C +25 C +125 C, -55 C
o o o o o o
LIMITS MIN 1 .74 MAX 720 972 200 270 UNITS ns ns ns ns MHz MHz
PARAMETER Propagation Delay Clock to Shift Left/Right Output Transition Time
SYMBOL TPHL TPLH TTHL TTLH FCL
CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND
Maximum Clock Input Frequency NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55o C, +25 C
o o
MIN -
MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2
UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA
+125 C VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125 C VDD = 15V, VIN = VDD or GND 1, 2 -55 C, +25 C +125 C Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25 C, +125 C, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC
o o o o o o o o
4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 -
7-1279
Specifications CD40100BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage Low Input Voltage High Propagation Delay Clock to Shift Left/Right Output Transition Time SYMBOL VIL VIH TPHL1 TPLH1 TTHL CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V Maximum Clock Input Frequency Minimum Data Setup Time FCL VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V Minimum Data Hold Time TH VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width Low Level TWL VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width High Level TWH VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 UNITS A V V V V V CIN Any Input NOTES 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +7 2.5 3 330 230 100 80 100 20 10 275 100 75 450 230 190 280 150 140 7.5 V ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns pF MIN MAX 3 UNITS V
7-1280
Specifications CD40100BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Propagation Delay Time SYMBOL TPHL TPLH CONDITIONS VDD = 5V NOTES 1, 2, 3, 4 TEMPERATURE +25oC MIN MAX 1.35 x +25oC Limit UNITS ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) ON Resistance SYMBOL IDD IOL5 IOH5A RONDEL10 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 OPEN 1, 4, 5, 7, 10, 12, 14, 15 1, 4, 5, 7, 10, 12, 14, 15 1, 5, 7, 10, 14, 15 1, 4, 5, 7, 10, 12, 14, 15 GROUND 2, 3, 6, 8, 9, 11, 13 8 2, 8, 13 8 VDD 16 2, 3, 6, 9, 11, 13, 16 9, 16 2, 3, 6, 9, 11, 13, 16 4, 12 3 6, 11 9V -0.5V 50kHz 25kHz
7-1281
Specifications CD40100BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued) OSCILLATOR FUNCTION NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN GROUND VDD 9V -0.5V 50kHz 25kHz
TABLE 9. DATA TRANSFER TABLE* INITIAL STATE CLOCK RESULTING STATE INTERNAL STAGE Q 0 NC 1 NC X NC
DATA INPUT 0 X 1 X X 0 = Low Level
CLOCK INHIBIT 0 0 0 0 1
INTERNAL STAGE X 0 X 1 1 NC = No Change
LEVEL CHANGE
OUTPUT NC 0 NC 1 NC
1 = High Level
X = Don't Care
* For Shift-Right Mode Data Input = SHIFT RIGHT INPUT (Term. 11) Internal Stage = Stage 1 (Q1) Output = SHIFT LEFT OUTPUT (Term. 4) For Shift Left Mode Data Input = SHIFT LEFT INPUT (Term. 6) Internal Stage = Stage 32 (Q32) Output = SHIFT RIGHT OUTPUT (Term. 12) TABLE 10. CONTROL TRUTH TABLE LEFT/RIGHT CONTROL 1 1 0 0 X RECIRCULATE CONTROL 1 0 1 0 X
CLOCK INHIBIT 0 0 0 0 1
ACTION Shift Left Shift Left Shift Right Shift Right No Shift
INPUT BIT ORIGIN Shift Left Input Stage 1 Shift Right Input Stage 32 -
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
1282
CD40100BMS Logic Diagram
CLOCK 3* CLOCK INHIBIT 2* SHIFT RIGHT 11* INPUT R p n LEFT/RIGHT 13* CONTROL R S S S S p RECIRCULATE 9* CONTROL R R n S R p n S p n
CL CL
CL p
SHIFT RIGHT 12 OUTPUT
S S p n
CL
CL
S p n S
n CL
CL p n CL
STAGE 1
CL
CL
S p
STAGE 2
n S
STAGES 3-30 (ALL IDENTICAL TO STAGES 2 AND 31)
S VDD p n S CL VSS p n CL CL p n CL SHIFT LEFT 6* INPUT
CL
CL
S p n S
STAGE 31
CL
CL
S p
R p n R p n R SHIFT RIGHT 12 OUTPUT
STAGE 32
*
ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK
n S
CL p n CL CL p n CL
CL p n CL CL p n CL
D
Q
FIGURE 1.
7-1283
CD40100BMS Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -5 -10 -15 -10V -20 -25 -15V -30
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-10
-15V
-15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 600 SUPPLY VOLTAGE (VDD) = 5V 400
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
200 SUPPLY VOLTAGE (VDD) = 5V
150
200
100 10V 50 15V
10V
15V 0 20 40 60 80 100
0 0
20
LOAD CAPACITANCE (CL) (pF)
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME (CLOCK TO SHIFT LEFT/RIGHT) AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
7-1284
CD40100BMS Typical Performance Characteristics
8 6 4 2 8 6 4 2
(Continued)
SUPPLY VOLTAGE (VDD) = 15V
105
CL = 50pF CL =15pF
104
8 6 4 2 8 6 4 2 2 4 68 2 4 68 2
10V 10V 5V
103
102
4 68
2
4 68
1
10
102
103
104
CLOCK INPUT FREQUENCY (fCL) (KHz)
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY
Timing Diagram
tWL tWH CLOCK tS tH INPUT tPHL OUTPUT tPHL
FIGURE 9. TIMING DIAGRAM DEFINING SETUP, HOLD, AND PROPAGATION DELAY TIMES
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kA - 14kA, PASSIVATION: 10.4kA - 15.6kA, Silane
AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (RL) = 200K INPUT RISE & FALL TIME (tr, tf) = 20ns
2 4 68
POWER DISSIPATION (PD) (W)
AL.
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1285

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